Memory is utilized in modern computing architectures for storing data. One type of memory is Dynamic Random-Access Memory (DRAM). DRAM may provide advantages of structural simplicity, low cost and high speed in comparison to alternative types of memory.
DRAM may utilize memory cells which have one capacitor in combination with one transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. An example 1T-1C memory cell 2 is shown in FIG. 1, with the transistor labeled T and the capacitor labeled C. The capacitor has one node coupled with a source/drain region of the transistor, and has another node coupled with a common plate, CP. The common plate may be coupled with any suitable voltage, such as a voltage within a range of from greater than or equal to ground to less than or equal to VCC (i.e., ground≤CP≤VCC). In some applications, the common plate is at a voltage of about one-half VCC (i.e., about VCC/2). The transistor has a gate coupled to a wordline WL (i.e., access line), and has a source/drain region coupled to a bitline BL (i.e., digit-line or sense line). In operation, an electric field generated by voltage along the wordline may gatedly couple the bitline to the capacitor during read/write operations.
Another prior art 1T-1C memory cell configuration is shown in FIG. 2. The configuration of FIG. 2 shows two memory cells 2a and 2b; with the memory cell 2a comprising a transistor T1 and a capacitor C1, and with the memory cell 2b comprising a transistor T2 and a capacitor C2. Wordlines WL0 and WL1 are electrically coupled with the gates of transistors T1 and T2, respectively. A connection to a bitline BL is shared by the memory cells 2a and 2b. 
The memory cells described above may be incorporated into memory arrays, and in some applications the memory arrays may have open bitline arrangements. An example integrated assembly 9 having open bitline architecture is shown in FIG. 3. The assembly 9 includes two laterally adjacent memory arrays (“Array 1” and “Array 2”), with each of the arrays including memory cells of the type described in FIG. 2 (not labeled in FIG. 3 in order to simplify the drawing). Wordlines WL0-WL7 extend across the arrays, and are coupled with wordline drivers. Digit-lines D0-D8 are associated with the first array (Array 1), and digit-lines D0*-D8* are associated with the second array (Array 2). Sense amplifiers SA0-SA8 are provided between the first and second arrays. Digit-lines at the same height are paired within one another and compared through a sense amplifier (e.g., digit-lines D0 and D0* are paired with one another and compared with the sense amplifier SA0). In a read operation, one of the paired digit-lines may serve as a reference in determining electrical properties (e.g., voltage) of the other of the paired digit-lines.
A continuing goal of integrated circuit fabrication is to increase integration. There is interest in stacking decks (tiers) of integrated circuitry to achieve high integration. However, it is proving difficult to couple circuitry from upper decks with the circuitry of lower decks, particularly since there is generally at least some risk of misalignment of the decks. It would be desirable to develop three-dimensional arrangements enabling coupling of the circuitry from upper decks to lower decks, and enabling the ability to correct for possible misalignment.